\vspace{10pt}
\section{Thermomechanical Stress-aware 3D Design and Management}\label{sec:framework}
In this section, we present detail explanation of the proposed design-time thermal stress-aware placement technique to minimize thermal induced mechanical stress around TSVs and run-time thermal management method to achieve mechanical equilibrium thermal cycling pattern.

\subsection{Placement Optimization Objective}
During early stages of the design cycle, designers have limited accurate information on on-chip temperature. The objective of the design-time thermal stress-aware management is to reduce the CTE induced thermomechanical stress on TSVs. From equation \ref{eq:stress_tsv}, the thermal stresses are proportional to the thermal load on TSV farms, which translates into the minimization of the TSVs thermal load. Intuitively, for thermal stress minimization, TSV farms should move away from hot regions to reduce their thermal load. However, under most cases, the hotspots are high utilized functional units with high connectivity requirements. Moving TSV farms away from heat sources results in increased wire length and communication delay, which will degrade performance. To balance the tradeoff between performance and TSV induced thermal stresses, in this work, the wire length and chip area are taken into consideration for thermal stress-aware TSVs placement. 

\subsection{Thermomechanical Stress-aware Placement Flow}
The proposed placement flow optimizes traditional area and performance driven placement solutions by incorporating thermal induced stresses minimization. The detail of the flow is shown in Fig. \ref{fig:design flow}. Circuit description and average power consumption of each block are given as input. The average power consumption of each block is estimated from the assumed power density on the chip during design time when the actual block activity factor is unknown. The circuit description contains two parts: the first part is the block descriptions, includes the block name, area and allowable aspect ratio (minimum and maximum aspect ratio during placement); the second part includes the connectivity information. Final optimized placement is given as output. TSV farms are treated as soft blocks in the placement with given thermal characteristics described in section \ref{sec:bkground}.

\begin{figure}[htbp]
\centering
\includegraphics[width=0.40\textwidth]{figures/design_time_flow.pdf}
%\vspace{-5pt}
\caption{Design Time TSV Farm Placement Flow}\label{fig:design flow}
\vspace{-15pt}
\end{figure}

A simulated annealing based placer is used in the flow incorporating with an analytical initial placement to speed up the convergence. First, the circuit is partitioned into required tiers by balancing the TSV number and chip area, then initial placement is performed. Since the temperature is highly depended on the power density of the module. Initial placement is generated analytically by placing low power density modules around TSV farm. The TSV and tier temperature is estimated for initial cost calculation. After initial stage, modules are selected to swap with other modules within the same layer or between different tiers. Besides changing module position, the aspect ratio of module can be adjusted. For TSV, changing the aspect ratio of TSV farm means adjusting the arrangement of fixed number TSVs. By adjusting the arrangement of TSVs, the lateral thermal path is changed for better heat dissipation. 
 
%The algorithm of the simulated annealing placer is shown in Algorithm \ref{alg:saengine}. A random floorplan is generated for initialization, then for each step, a new floorplan is generated by permuting the location of TSV farms or changing the aspect ratio of TSV farms. The new cost associated with the floorplan is calculated to compare with previous result. If the cost is smaller than previous one, then this new solution is accepted with probability determined by both T (temperature in simulated annealing engine) and cost difference ($\Delta c$). When the cost is larger than previous one, the solution is rejected. After each solution generation, the value of T decreases by a default ratio. The process repeats until T is below a threshold or maximum steps are achieved. 
A cost function is incorporated to optimize the placement during simulated annealing iterations. After each iteration, the cost is calculated based on the estimated thermal profile. If the solution is better than previous solutions, the new solution is recorded. The whole program terminates when the SA convergence condition is satisfied or maximum iteration step is achieved. In our flow, the program is converged when the simulated temperature is low enough or the solution reject rate is higher than predetermined rate.

%\begin{algorithm}                     
%\caption{Outline of the simulated annealing based placement algorithm with TSV-farm reshape or relocate}    
%\label{alg:saengine}                           % and a label for \ref{} commands later in the document
%\begin{algorithmic}                    % enter the algorithmic environment
%  \STATE  SA Placement Algorithm  
%   
%    \COMMENT{Initialization}
% \STATE   Initial floorplan $S_{best} \leftarrow S$, temperature $T > 0$; 
%    \WHILE{$T > T_{threshold}$ and $step < step_{MAX}$}
%\STATE Randomly pick one TSV-farm structure form S;
%\STATE Generate a random number i between 0 to 1;
%\IF{$i < 0.5$}
%\STATE Change TSV's aspect ratio;
%\ELSE
%\STATE Relocate TSV farm;
% \ENDIF
% \STATE Update S';
%\STATE Calculate cost $c(S')$;
%\STATE $\Delta c = c(S') - c(S)$;
%\IF {$\Delta c < 0$}
%\STATE Reject S';
%\ELSE
%\STATE $S \leftarrow S'$ with the probability $e^{-\Delta c/T}$;
%\ENDIF
%\IF {$c(S_{best}) > c(S')$}
%\STATE $S_{best} \leftarrow S'$;
%\ENDIF
%\STATE $c(S_{best})$ = c(S');
%\STATE T = rT; 
%    \COMMENT {$r<1$}
%\ENDWHILE
%\end{algorithmic}
%\end{algorithm}

The associated cost function is given as following:
\begin{equation}\label{eq:costfunc}
Cost = \alpha * A + \beta * T_{average} + \gamma * T_{TSV} + \delta* W 
\end{equation}
where $\alpha$, $\beta$, $\gamma$ and $\delta$ are associated weighting parameters, A is the final chip area, $T_{max}$ is the average temperature among blocks, $T_{TSV}$ is the estimated average temperature of TSV farms to represent the thermal stresses, and W is the wirelength in the design. 

As illustrated above, in order to maintain the allowable performance, silicon area and wirelength are integrated into the cost function. The peak temperature of blocks in the placement is also an important metric since local hotspot with significant high temperature can result in mechanical imbalance on the chip. The TSV temperature is the major metric to guide the placement to minimize the interfacial delamination and cracking between TSVs and nearby components. 

\subsection{Thermal Cycling-aware Run-time Management}
Run-time thermal cycling management technique is proposed as the second stage of thermal management to achieve 3D architecture mechanical equilibrium by eliminating mechanical damaging thermal cycling patterns as illustrated in section \ref{sec:bkground}. 

The run-time management is performed on each tier for whole stack. The stack is partitioned into several small grids, and the temperature of each grid is monitored during runtime. Given the power trace that considers the supply voltage and activity factor of each blocks, a dynamic thermal profile can be obtained for temperature monitoring during runtime thermal management. Proposed dynamic management framework is given in Fig. \ref{fig:runtime flow}. After a certain sampling interval, the grid temperature on each tier is captured and the temperature gradients are analyzed. The temperature differences between grids are used to represent temperature gradients for simplicity. 

The first step controls the temperature gradients of each grid to avoid large temperature differences between adjacent grids. For each grid, the temperature differences in x, y, and z directions are calculated. Corresponding mechanical force vectors are derived from temperature gradients information for each grid. The force vectors are compared with predetermined thresholds for 3D architecture. The predetermined thresholds are customized based on the TSV size, material, and substrate thickness. If the force vectors are larger than thresholds, the power scaling technique is used to control the thermal dissipation of hotter grids. In the proposed run-time management, dynamic voltage and frequency scaling (DVFS) is adapted. 
\begin{figure}
\centering
\includegraphics[width=0.45\textwidth]{figures/dynamic_flow.pdf}
%\vspace{-5pt}
\caption{Run-time Thermal Cycling-aware Thermal Management Flow}\label{fig:runtime flow}
%\vspace{-15pt}
\end{figure}

If none of the force vectors from previous step exceeds the thresholds. The second step takes place to control the thermal cycling pattern. The cycling pattern is analyzed by comparing the force vectors with neighboring grids of two adjacent layers. If the thermal cycling pattern is in an alternating way as described in Fig. \ref{fig:cycling pattern}, which cause opposite direction of forces between neighbors, dynamic power management takes place on interested regions to lower the resulting thermal mechanical stresses and achieve mechanical equilibrium. For example, in Fig. \ref{fig:cycling pattern}, the top middle grid has mechanical force in opposite direction with its neighbors, resulting in cracking on thinned silicon with this inverting heating patterns. The proposed run-time technique lower the temperature of the upper block using power scaling to minimize the risk of cracking. The power scaling results in new mechanical force pattern in the stacks, so the temperature gradients estimation continues until the whole stack reaches the steady state. 

%how to integrate with hotspot